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SGP refers to Selective Gold Process, meaning that the Ni/Au plating process has been applied only on the finger area. There is no Ni/Au plating on trace pattern surfaces.
ASE BGA's design and features improve the performance of graphic ICs, PLDs, DSPs, PC chipsets, communications, networking, microprocessors/controllers, ASIC, gate arrays and memory packages.
What is so unique about the SGO design is that it has no plating bus, which results in the following:
• Better electrical performance in high-frequency.
• Higher density in substrate pattern design.
• Open/Short Test can be applied in substrate suppliers for matrix substrate type.
Package Level
Lead Free
BOM
(260°C) |
MSL |
JEDEC Level 3, 30°C/60% RH |
192 hours |
| TCT |
-65°C~150°C |
100 cycles |
| HAST |
130°C/85%RH/33.5 psig |
96 hours |
| HTST |
150°C |
1000 hours |
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